1. Field
This invention relates to a device, method, medium for verification scenario generation that is used in verification.
2. Description of the Related Art
Logic verification using which verification of whether an integrated circuit is normally operated is indispensable for designing the integrated circuit (for example, a large scale integrated circuit (LSI)). The logic verification is also important in order to keep high quality of, especially, the LSI for which a larger scale, a higher functionality, a higher speed, and a lower power consumption is generally required. On the other hand, a higher efficiency in working has been required by a shorter design period for the LSI in a conventional manner.
A typical verification system for an integrated circuit will be explained, referring to FIG. 20. Review information 103 and verification property (assertion group) 104 are made from specifications 101 for a circuit to be verified by conversion processing 102 based on manual operation by an operator (for example a designer) in a verification system 100 while the specifications 101 is made by the operator. Then, the operator may review the specification 101 by feeding back the review information 103 thereto.
Moreover, the logic verification of the circuit to be verified is performed by a verification unit 107, based on the verification property 104 obtained by the conversion processing 102 based on manual operation by the operator, a verification scenario (verification environment scenario) 105, and circuit information 106 on the circuit to be verified.
However, a verification environment of verification items and the verification scenario 105, and the like, which are required for logic verification of an integrated circuit, have been typically made from a specification described in a natural language, based on manual operation by an operator performing logic verification.
Accordingly, a more complicated function, and a more highly integrated structure of integrated circuits have recently required a huge amount of man-hours as a result of manual operations of the operator, thereby putting an enormous load on the operator. Moreover, there has been often cases in which remaking or repeating of the verification scenario is necessary due to elimination of or errors in verification items and the like, where the elimination and the errors are caused by manual operations of the operator. When the verification scenario is remade, a longer design period, and a higher cost for development of the integrated circuit are required.
Accordingly, reduced man-hours of manual operations by the operator, a lighter load on the operator, and, at the same time, need for less remaking of the verification scenario are subjects to be pursued.
Considering the above discussed and other existing problems, the present invention has been developed to reduce the load put on an operator, and, at the same time, reduce a time required for making a verification scenario when the verification scenario used for logic verification of an integrated circuit is made.